HBT transistors are used as signal generators in RADAR (RAdio Detection And Ranging) products, driving maximum switching frequencies of in excess of 400 GHz in order to fulfill the demand for better spatial and velocity resolution at reduced power consumption. It is desired to increase the maximum available switching frequency (fMax) by 50% or more. However, this increase cannot be achieved with currently available, production-worthy device concepts. In order to increase switching speed, the parasitic elements of the device have to be reduced or eliminated beyond the current device architecture.
While increasing performance of the devices, cost of production is to be reduced, e.g. by factor two. The cost adder of the current architecture is mainly owed to four additional lithography levels (EW (emitter window), BA (base link), DA (emitter contact landing pad), EA (bipolar transistor to metallization contact structure)) using expensive deep-UV (ultra violet) lithographic processes and associated structuring processes. In order to reduce cost, the process flow has to be simplified, critical process tolerances need to be reduced or eliminated in order to improve yield potential.
In other words, HBT (Hetero junction Bipolar Transistor) devices, that are used for applications operating in the multi GHz to THz range have to meet a number of competing and conflicting requirements with respect to switching speeds (figures of merit e.g. fMax, ringo-delay tau) with small tolerances, while keeping manufacturing cost low and yield high. The maximum oscillation frequency (fMax) is strongly influenced by the parasitic lead in resistance of the base region and parasitic overlap capacitances of the base/collector diode. High switching speeds also require steep doping profiles, limiting the additional thermal budget after the realization of the HBT device structure.